This invention relates to digital logic circuits of a digital computer, and more particularly, to a digital computer memory stack for storing return addresses whenever a subroutine or loop is executed.
In existing digital computer systems, stacks have been utilized for storing information in an automated, orderly manner to aid in reducing the time required to perform some of the various operations of a digital computer. Of particular interest is an implementation of a memory stack disclosed in U.S. Pat. No. 3,396,371, entitled "Controller for Data Processing System", by D. E. Waldecker. The referenced patent discloses a push-down memory in which the first memory position or first register, is designated the instruction counter. Information supplied to the pushdown memory is supplied through the first position, the information previously held in the first position being automatically transferred downward in the push-down memory. A branch or a jump instruction causes the address portion of the instruction plus one to be stored in the first position of the push-down memory, the return point of the main program (i.e., the current value in the instruction counter plus one) being pushed-down. A return instruction executed by the subroutine causes the return address of the main program to be pushed-up to the first position of the push-down memory, thereby effecting an orderly return to the main program. Each access of the push-down memory requires some finite amount of time slowing up the execution of the computer. The present invention is designed to enhance the operation of the processor by eliminating the memory stack access time with a minimum of additional hardware.